View FMS6408MTC_288216.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.fairchildsemi.com
FMS6408
Features
Triple Video Filter Driver for RGB and YUV Signals
Description
The FMS6408 provides three video signal paths including a two-input mux, a video filter and a 6dB gain output driver. The filter bandwidth supports RGB and YUV signals in either NTSC or PAL formats. The video filters approximate a 5th order Butterworth low pass characteristic optimized for minimum overshoot and flat group delay to provide excellent image quality. Four different peaking options are available. The video filters can be bypassed if desired. In a typical application, the RGB or YUV DAC outputs are AC coupled into the filters through the input mux. All channels have DC restore circuitry to clamp the DC input levels during video sync. The clamp pulse derived from the selected Y input controls three independent feedback clamps. All outputs are capable of driving 2Vpp, AC or DC coupled, into either a single (150) or dual (75) video load. The FMS6408 clamp levels can be factory programmed for YUV /RGB (250mV for all channels), YC / YPbPr (250mV on channel 1 and 1.125V on channels 2 and 3) or YC CV (250mV on channels 1 and 3 and 1.125V on channel 2). * 7.6MHz 5th order RGB/YUV/YC CV filters * 50dB stopband attenuation at 27MHz on all outputs * Better than 0.5dB flatness to 4.2MHz on all outputs * No external frequency selection components or clocks * AC coupled inputs and AC or DC coupled outputs * Supports both NTSC and PAL luminance bandwidth * Continuous time low pass filters for video anti-aliasing or reconstruction applications * <1% differential gain with 0.5 differential phase on all channels * Integrated DC restore circuitry with low tilt
Applications
* Cable set top boxes * Satellite set top boxes * Terrestrial set top boxes * DVD players * Personal Video Recorders (PVR) * Video On Demand (VOD)
Functional Block Diagram
INMUX (A/B) BYPASS (BYPASS/FILTER)
YINA YINB 8MHz*
6dB
YOUT
gM
250mV Sync Processing
UINA UINB 8MHz*
6dB
UOUT
gM
250mV or 1.125V *
VINA VINB 8MHz*
6dB
VOUT
gM
* Factory Selected Clamp and Peaking Levels
250mV or 1.125V *
REV. 2C August 31, 2004
DATA SHEET
FMS6408
Electrical Specifications
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz, 0dB peaking option; unless otherwise noted) Symbol ICC Vi Vil Vih VCLAMP PSRR Parameter Supply Current1 Input Voltage Max Digital Input Low1 Digital Input Clamp High1 Voltage2 Bypass, A_NB Bypass, A_NB YUV/RGB/CV Inputs PbPr/C Inputs Power Supply Rejection Ratio DC 0 2.0 250 1.125 -40 Conditions VCC no load Min Typ 52 1.4 0.8 VCC Max Units 86 mA Vpp V V mV V dB
AC Electrical Specifications
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz, 0dB peaking option; unless otherwise noted) Symbol APB AVLF AVHF Parameter Passband Response1 Low Frequency Gain (All Channels) Delta High Frequency at 5MHz (All Channels)3
1
Conditions 4.2MHz at 400kHz 0dB Peaking Option 0.4dB Peaking Option 0.9dB Peaking Option 1.3dB Peaking Option
Min -0.5 5.6
Typ 0 5.9 0.3 0.7 1.2 1.6 7.6
Max Units dB 6.2 dB dB dB dB dB MHz dB % %
dB
fC fSBh dG d THD SNR HDIST VDIST tpd GD tSKEW AV(match) TCLAMP XTALK INMUXISO f1dBWB
-3dB Bandwidth Stopband Rejection (All Channels) Differential Gain Differential Phase Total Harmonic Distortion Line-Time Distortion Field-Time Distortion Propagation Delay (All Channels) Group Delay (All Channels) tpdSkew Between Any 2 Channels Channel Gain Matching1 Crosstalk (Channel-to-Channel) Input Mux Isolation Bypass Mode -1dB Bandwidth
1
All Channels at 27MHz All Channels All Channels at 3.58MHz 18s, 100 IRE Bar 130 Lines, 18s, 100 IRE Bar 400kHz to 3.58MHz (NTSC) at 400kHz 400kHz at 1.0MHz at 1.0MHz 1.4Vpp Output All Channels 48
52 0.2 0.5 0.2 75 TBD TBD 65 14 2 0 5 -65 -85 25 5
SNR All Channels (NTC7 Weighted) 4.2MHz Lowpass, 100kHz Highpass
% % ns ns ns % ms dB dB MHz
Clamp Response Time (All Channels) Settled to 10mV, Initial Condition 0V
Notes 1. 100% tested at 25C. 2. Mode selection for YUV/RGB vs. PbPr/YC vs. YC CV operation based on factory programming 3. Peaking Options boost gain by 0dB, 0.4dB, 0.9dB, or 1.3dB from 4.2MHz to 5MHz based on factory programming
2
REV. 2C August 31, 2004
FMS6408
DATA SHEET
Factory Programming Options (See Ordering Information Table on Page 9 for current options)
Part Name FMS6408-1 FMS6408-2 FMS6408-3 FMS6408-4 FMS6408-5 FMS6408-6 FMS6408-7 FMS6408-8 FMS6408-9 FMS6408-10 FMS6408-11 FMS6408-12 Part Number
FMS6408MTC141_NL FMS6408MTC142_NL FMS6408MTC143_NL FMS6408MTC144_NL FMS6408MTC145_NL FMS6408MTC146_NL FMS6408MTC147_NL FMS6408MTC148_NL FMS6408MTC149_NL FMS6408MTC1410_NL FMS6408MTC1411_NL FMS6408MTC1412_NL
Clamping Mode
YPbPr/YC YPbPr/YC YPbPr/YC YPbPr/YC YUV/RGB YUV/RGB YUV/RGB YUV/RGB YC/CV YC/CV YC/CV YC/CV
Peaking Mode (dB)
0 0.4 0.9 1.3 0 0.4 0.9 1.3 0 0.4 0.9 1.3
YOUT Level (mV)
250 250 250 250 250 250 250 250 250 250 250 250
UOUT Level (V)
1.125 1.125 1.125 1.125 250 250 250 250 1.125 1.125 1.125 1.125
VOUT Level (V)
1.125 1.125 1.125 1.125 250 250 250 250 250 250 250 250
Note These factory programming options allow a single die to be configured for multiple operating modes.
Absolute Maximum Ratings (beyond which the device may be damaged)
Parameter VCC Analog and Digital Output Current Any One Channel (Do not exceed) Input Source Resistance (RS) Min -0.3 -0.3 Max 6 VCC + 0.3 50 300 Units V V mA
Note Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded.
Reliability Information
Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance (JA), JEDEC Standard Multi-layer Test Boards, Still Air 90 -65 Min Typ Max +150 +150 +300 Units C C C C/W
Recommended Operating Conditions
Parameter Temperature Range VCC Range Min 0 +4.75 +5.0 Typ Max 70 +5.25 Units C V
REV. 2C August 31, 2004
3
DATA SHEET
FMS6408
Typical Performance Characteristics
(TC = 25C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1F, all outputs AC coupled with 220F into 150, referenced to 400kHz, 0dB peaking option; unless otherwise noted)
SD Frequency Response
10 0
1 2
SD Group Delay vs. Frequency
60 40
Gain (10dB/div)
-20
Mkr Freq. Gain
Delay (ns)
-10
20 0 -20 -40
1
-30 -40 -50
Ref 400kHz 6dB 1 6.91MHz -1dB BW 2 3 7.8MHz 27MHz -3dB BW -43.24dB 3
fSBSD = Gain(ref) - Gain(3) = 49.24dB
1 = 7.6MHz (31.88ns)
-60 30 400kHz 5 10 15 20 25 30
400kHz
5
10
15
20
25
Frequency (MHz) SD Noise vs. Frequency
-50 -60 0.2
Frequency (MHz) SD Differential Gain
NTSC
Differential Gain (%)
0 -0.2 -0.4 -0.6 -0.8
-70
Noise (dB)
-80 -90 -100 -110 -120 0 1.0 2.0 3.0 4.0 5.0 6.0
Min = -0.61 Max = 0.00 ppMax = 0.61
1st
2nd
3rd
4th
5th
6th
Frequency (MHz)
SD Differential Phase
0.05 7
Bypass Mode Frequency Response
VO = 1.4pp
Differential Phase (deg)
0
6
Gain (1dB/div)
5
1
-0.05 -0.10 -0.15 -0.20 1st 2nd 3rd 4th 5th 6th
4
2
3 2 1 0 400kHz 5 10 15 20 25 30 35 40 45
Mkr Ref 1 2 Frequency 400kHz 28.75MHz 36.94MHz Gain 6dB -1dB BW -3dB BW
Min = -0.13 Max = 0.00 ppMax = 0.13
Frequency (MHz) Bypass Mode Group Delay vs. Freq.
16 14 12
Delay (ns)
10 8 6 4 2
1 = 25MHz (8.99ns) 1
0 400kHz 5 10 15 20 25 30 35 40 45
Frequency (MHz)
4
REV. 2C August 31, 2004
FMS6408
DATA SHEET
Pin Configuration
Pin#
YINA UINA VINA
Pin YINA UINA VINA GND YINB UINB VINB INMUX (A/B) VOUT GND UOUT BYPASS (Bypass/Filter) YOUT VCC
Type Input Input Input Input Input Input Input Input Output Input Output Input Output Input
Description Y (Luminance) or Green input A, must be connected to a signal which includes sync U or Blue input A V or Red input A Must be tied to ground, do not float Y (Luminance) or Green input B, must be connected to a signal which includes sync U or Blue input B V or Red input B Mux select, A = `1', B = `0', must be externally tied high or low V or Red output Must to be tied to ground, do not float U or Blue output Filter bypass, BYPASS = `1', FILTER = `0', must be externally tied high or low Y or Green output +5V supply
1 2 3 4 5 6 7
14
VCC YOUT BYPASS UOUT GND VOUT
1 2 3 4 5 6
FMS6408 14-pin TSSOP
13 12 11 10 9 8
GND Y
INB
UINB VINB
INMUX (A/B)
7 8 9 10 11 12 13 14
Functional Description
Introduction
This product is a three channel monolithic continuous time video filter designed for reconstructing YUV, YC CV or RGB signals from a video D/A source. Inputs should be AC coupled while outputs can be either AC or DC coupled. The reconstruction filters approximate a 5th order Butterworth response optimized for minimum overshoot and flat group delay. This provides a maximally flat response in terms of delay and amplitude. Each of the three outputs is capable of driving 2Vpp into 75 loads. All channels are clamped during the sync interval to set the appropriate dc output level. Sync tip clamping greatly reduces the effective input time constant allowing the use of small low cost input coupling capacitors. The input will settle to 10mV in 2ms for typical DC shifts present in the video signal. In most applications the input coupling capacitors are 0.1F. The inputs typically sink 1uA of current during active video. For YUV signals, this translates into a 2mV tilt in a horizontal line at the Y output. During sync, the clamp restores this leakage current by sourcing an average of 20A over the clamp interval. Any change in the coupling capacitor values will affect the amount of tilt per line. Any reduction in tilt will come with an increase in settling time.
Sync processing is based on the Y/G input channel in all operating modes.
Inputs
The inputs will typically be driven by either a low impedance source of 1Vpp or the output of a 75 terminated line driven by the output of a current DAC. In either case, the inputs must be capacitively coupled to allow the sync-detect and DC restore circuitry to operate properly.
Outputs
The outputs are low impedance voltage drivers which can handle either a single or dual load. A single load consists of a 75 series termination resistor feeding a 75 terminated line for a total load at the part of 150. Even when two loads are present (75) the driver will produce a full 2Vpp signal at its output pin. The driver can also be used to drive an AC coupled single or dual load. When driving a dual load either output will still function if the other output connection is inadvertently shorted providing these loads are AC coupled.
REV. 2C August 31, 2004
5
DATA SHEET
FMS6408
Typical Application Diagrams
+5V 0.1 uF 1.0 uF
0.1uF
1 YINA YINA V CC FMS6408 14L TSSOP 2 UINA UINA YOUT 13 14
0.1uF
220uF
0.1uF
3 VINA VINA BYPASS 12
220uF
4 GND UOUT 11
300k 0.1uF
5 YINB YINB GND 10
0.1uF
6 UINB UINB VOUT 9
220uF
0.1uF
7 VINB VINB INMUX (A/B) 8
10k
Figure 1. AC-Coupled YUV Line Driver with Single Video Loads
+5V 0.1 uF 0.1uF
YINA
1.0 uF 75 Video Cables 75
YOUT 13
1
YINA FMS6408 14L TSSOP UINA
14
V CC
75
0.1uF
UINA
2
75 75
0.1uF
VINA
3
VINA
BYPASS
12
75 75
4
GND
UOUT
11
75 75 75 75
300k
0.1uF
YINB
5
Y
INB
GND
10
0.1uF
UINB
6
UINB
VOUT
9
75 75
0.1uF
VINB
10k
7 VINB 8
INMUX (A/B)
Figure 2. DC-Coupled YUV Line Driver with Dual Video Loads
6
REV. 2C August 31, 2004
FMS6408
DATA SHEET
Application Notes
Output Drive Capability
The FMS6408 can drive dual 75 loads where each load consists of a 75 resistor in series with a 75 termination resistor in the driven device. This presents a 150 load to the output so two similar loads in parallel look like 75 from the output to ground. In some cases it may be desirable to drive a single load on one or more outputs with a dual load on the remaining outputs. This is an acceptable loading condition but might cause a slight degradation in gain matching.
Pdiss (Y) = (5V - 1.55V) * 20.6mA = 71mW The average DC level for the U and V channels is set by the clamp circuit to 1.125V. The signal will be symmetrical about this voltage so: Iload (U) = 1.125V/75 = 15mA The device dissipation due to this load will be the internal voltage drop multiplied by the load current: Pdiss (U) = (5V - 1.125V) * 15mA = 58.125mW Since the U and V power dissipation are approximately the same, the total dissipation due to the load can be estimated by: Pdiss (load) = P (Y) + 2 * P (U) = 71mW + (2 * 58.125mW) = 187.55mW This will bring the typical total device power dissipation to 260mW (quiescent power) + 187.55mW (load power) or 447.55mW. It is advisable to calculate the highest possible power dissipation using worst-case quiescent supply current and the maximum allowable power supply voltage. This result should be used when calculating the die temperature rise with the supplied JA, thermal resistance value.
Device Power Dissipation
The FMS6408 specifications provide a quiescent no-load supply current of 52mA (typical). With a nominal 5V supply, this results in a power dissipation of 260mW. The overall power dissipation can be significantly affected by the applied load, particularly in DC-coupled applications. In order to calculate the total power dissipation the typical output voltages and the loading must be known. The highest power dissipation will occur for YUV video signals that are DC-coupled into dual video loads. Refer to the the diagram in Figure 3 below. Assume a video signal on the Y channel that averages 50% luminance with an output voltage of 1.55V then calculate the load current: Iload (Y) = 1.55V/75 = 20.6mA The device dissipation due to this load will be the internal voltage drop multiplied by the load current:
+5V
Field Time Distortion
In applications with AC-coupled outputs, the AC-coupling capacitors will dominate the field time distortion. Performance is specified with 220F coupling capacitors; if better performance is desired, the capacitors may be increased or the outputs may be DC-coupled.
VCC
2.25V 1.55V
75
75 Video Cables
IY Driver + VIY YOUT
75 75 75
0.85V 0.25V
1.825V 1.125V
75 75 75 75
IU Driver + VIU UOUT
0.425V
1.825V 1.125V
75 75 75 75
IV Driver + VIV VOUT
0.425V
Figure 3. YUV Video Signals that are DC-Coupled into Dual Video Loads
REV. 2C August 31, 2004
7
DATA SHEET
FMS6408
Package Dimensions
MTC-14
2X E/2 1.0 DIA 1.0 b1 ddd C B A
2X N/2 TIPS 123 6 6 N 5
e
-B-
7
(b)
8
MTC-14
c1 SYMBOL A A1 A2 L R R1 b b1 c c1 01 L1 aaa bbb ccc ddd e 02 03 D E1 E e N MIN - 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0 NOM - - 0.90 0.60 - - - 0.22 - - - 1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12 REF 12 REF 5.00 4.40 6.4 BSC 0.65 BSC 14 MAX 1.10 0.15 0.95 0.75 - - 0.30 0.25 0.20 0.16 8
E1 E
c
1.0
e /2 9
SECTION AA
ccc
7 -A-
D8 3
A2 A
aaa C
-C-
b NX bbb M C B A
A1
(02) (0.20) R1
-H-
R
GAGE PLANE 10
4.90 4.30
5.10 4.50
A A
0.25
(03)
L (L1)
01
NOTES:
1 All dimensions are in millimeters (angle in degrees).
2 3 4 5
Dimensioning and tolerancing per ASME Y14.5-1994. Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side . Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side. Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm for 0.5mm pitch packages. Terminal numbers are shown for reference only. Datums - A - and - B - to be determined at datum plane - H - . Dimensions "D" and "E1" to be determined at datum plane - H - . This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center" lead must be coincident with the package centerline, Datum A.
6 7 8 9
10 Cross sections A - A to be determined at 0.10 to 0.25mm from the leadtip.
8
REV. 2C August 31, 2004
FMS6408
DATA SHEET
Ordering Information
Model FMS6408 FMS6408 FMS6408 FMS6408 Part Number FMS6408MTC141_NL FMS6408MTC141X_NL FMS6408MTC143_NL FMS6408MTC143X_NL Lead Free Mode YUV/RGB YUV/RGB YUV/RGB YUV/RGB Output Peaking 0dB 0dB 0.9dB 0.9dB Package TSSOP-14 TSSOP-14 TSSOP-14 TSSOP-14 Container Tube Tape and Reel Tube Tape and Reel Pack Qty 94 2500 94 2500
Temperature range for all parts: 0C to +70C. Contact Fairchild for ordering information regarding other clamping and peaking options. Refer to the Factory Programming Options Table on page 3 for a detailed description of available options.
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to per form when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
(c) 2004 Fairchild Semiconductor Corporation

▲Up To Search▲

Price & Availability of FMS6408MTC

	To Download FMS6408MTC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .